Geometry.Net - Science: Temporal Logic

Temporal Logic In Information Systems
temporal logic in Information Systems. Jan Chomicki David Toman. Abstract Temporallogic is obtained by adding temporal connectives to a logic language.
http://www.brics.dk/LS/97/1/

Extractions: David Toman November 1997 Temporal logic is obtained by adding temporal connectives to a logic language. Explicit references to time are hidden inside the temporal connectives. Different variants of temporal logic use different sets of such connectives. In this chapter, we survey the fundamental varieties of temporal logic and describe their applications in information systems. Several features of temporal logic make it especially attractive as a query and integrity constraint language for temporal databases. First, because the references to time are hidden, queries and integrity constraints are formulated in an abstract, representation-independent way. Second, temporal logic is amenable to efficient implementation. Temporal logic queries can be translated to an algebraic language. Temporal logic constraints can be efficiently enforced using auxiliary stored information. More general languages, with explicit references to time, do not share these properties. Recent research has proposed various implementation techniques to make temporal logic practically useful in database applications. Also, the relationships between different varieties of temporal logic and between temporal logic and other temporal languages have been clarified. We report on these developments and outline some of the remaining open research problems.
Angelo Montanari Home Page
University of Udine Logical specifications of real-time systems, temporal and object-oriented databases, deductive databases, temporal representation and reasoning, modal and temporal logic, set theory.
http://www.dimi.uniud.it/~montana/index.html

Extractions: fax: ++39 0432 55-8499 Office: Room SN14 M.Sc. in Computer Science, University of Udine, April 1987, thesis : ``A distributed architecture for natural language processing. Quantification and reference'', under the supervision of Prof. Giovanni Guida. The thesis received a prize from IBM Italia as one of the best theses in computer science of the 1987. Ph.D. in Logic and Computer Science, University of Amsterdam, September 1996, thesis: ``Metric and Layered Temporal Logic for Time Granularity'', under the supervision of Prof. Johan van Benthem, University of Amsterdam and University of Stanford, and Prof. Alberto Policriti, University of Udine. 1987-1988 : Civil Service 1989-1991 : researcher at CISE - Tecnologie Innovative, Milano, Artificial Intelligence and Software Engineering Group. During this period, he was involved in national (CNR Project on Informatic Systems and Parallel Computation) and international (ESPRIT Project n. 2409 EQUATOR: an Environment for QUAlitative and TempOral Reasoning) research projects
Simin Nadjm-Tehrani
Link¶ping University Formal methods in verification of real-time and embedded systems, including discrete and hybrid models, applications of temporal logic, symbolic model checking, automata-based decompositional proof techniques.
http://www.ida.liu.se/~snt/
Kono's Temporal Logic Related Information
The summary for this Japanese page contains characters that cannot be correctly displayed in this language/character set.
http://rananim.ie.u-ryukyu.ac.jp/~kono/temporal-logic.html

Extractions: »þ¶è´Ö»þÁêÏÀÍý(Interval Temporal Logic)¤ò»È¤¤¿¤µ¤Þ¤¶¤Þ¤Ê¥×¥í¥¸¥§¥¯¥È ¤Ë´Ø¤¹¤ë¥Ú¡¼¥¸¤Ç¤¹¡£ English Page is here Tokio-9.94 Interval Temporal Logic ¤ò»È¤¤¿¥×¥í¥°¥é¥ß¥ó¥°¥Ä¡¼¥ë Tokio Programming Language RTL-Tokio Piplelined CPU verification tool LITE Intervale Temporal Logic Verifier TEMPORAL LOGIC PROGRAMMING LANGUAGE Tokio Shinji Kono, Tatsuya Aoyagi, Masahiro Fujita, Hidehiko Tanaka, Tatsuhiko Moto-oka
Theoretical Computer Science - Faculty
Institute of Mathematical Sciences, Chennai Theory of distributed systems, temporal logics, Partial order models of concurrency, Logics of knowledge.
http://www.imsc.ernet.in/~jam/
SRI International - Computer Science Laboratory - Ground Temporal Logic: A Logic
Publications Ground temporal logic A Logic for Hardware Verification by DavidCyrluk and Paliath Narendran. Lecture Notes in Computer Science, Volume 818.
http://www.csl.sri.com/papers/cav94/

Extractions: Abstract: We present a new temporal logic, GTL, appropriate for specifying properties of hardware at the register transfer level. We argue that this logic represents an improvement over model checking for some natural hardware verification problems. We show that the validity problem for this logic is Pi 1-1 complete. We then identify a fragment of the logic that is decidable. We show that in this fragment we are still able to encode many interesting problems, including the correctness of pipelined microprocessors. BibT E X entry:
Research Papers
University of Edinburgh Models and calculi for concurrent computation, modal and temporal logics with fixed points, verification and description of program properties.
http://www.dcs.ed.ac.uk/~cps/
TemporalRover
Provides automatic verification of protocols and reactive systems through temporal logic specifications.
http://www.time-rover.com/
Citations: The Temporal Logic Of Reactive And Concurrent Systems - Manna, Pnueli
Z. Manna and A. Pnueli. The temporal logic of Reactive and Concurrent Systems. Thetemporal logic of Reactive and Concurrent SystemsSpecification.
http://citeseer.nj.nec.com/context/9751/0

Extractions: A Theory for Composing Distributed - On (Correct) ....fairness, Q can go back and forth indefinitely between states in J 1 #J 2 and J 1 J 2 and this can block P s progress to q. In For these we refer the reader to standard textbooks, e.g. Some adjustments, however, to these laws are needed to cope with the J and the V parameters. The reformulation of some commonly used UNITY laws [5] is given in Appendix A. 3.7 The J Parameter: Stable or Invariant If the reader is familiar with the Sanders work [21] he or she might recognize ....
Citations: The Temporal Logic Of Programs - Pnueli (ResearchIndex)
Similar pages More results from citeseer.nj.nec.com developerWorks Java technology Diagnosing Java code One way to fill this gap is with temporal logic, a formalism usedto describe how a program state will change over time. In this
http://citeseer.nj.nec.com/context/18303/0

Extractions: Design Validation of ZCSP with SPIN - Differents Models And (Correct) through typed bu ered channels, through shared variablesorany combination of these [4] SPIN accepts design speci cations written in the veri cation language ProMeLa (a Process Meta Language) and it accepts correctness claims speci ed in the syntax of standard Linear Temporal Logic (LTL) The result is again a B uchi .... A. Pnueli. The Temporal Logic of Programs Software Tools for Technology Transfer manuscript iNTo. - Will Be Inserted (Correct) ....written in high level logics by users of the system. Logics are currently imple mented in Maude [6] a high performance system sup porting both rewriting logic and membership equational logic. One can naturally and easily define new logics in Maude, such as for example temporal logics , to gether with their finite trace operational semantics.
DeveloperWorks: Java Technology : Diagnosing Java Code: Using Temporal Logic Wit
temporal logic is a formalism used to describe how a program state will changeover time. Diagnosing Java code Using temporal logic with bug patterns,
http://www-106.ibm.com/developerworks/java/library/j-diag0827.html?dwzone=java
Dept. Of AI: Alumni
University of Ulm Object-oriented approaches to formal specification and verification, formal specification and verification of reactive systems, component-based formal development of concurrent systems, and the temporal logic of Actions.
http://www.informatik.uni-ulm.de/ki/canver.html

Extractions: University of Ulm Faculty of Computer Science Dept. of Artificial Intelligence back: Staff Alumni Ercüment Canver Ercuement .Canver @icn. siemens.de joined Siemens AG, Ulm Daniela Damm damm@ifi.unizh.ch Dr. Axel Dold dold@tescom.de or axel.dold@gmx.de joined TESCOM GmbH, Ulm Andrea Hemprich hemprich@io-software.com joined IO Software, Freiburg Martin Hiller Martin.Hiller@t-systems.de joined T-Systems/Debis, Ulm Alke Martens ... alke.martens@informatik.uni-rostock.de joined Univ. of Rostock Prof. Dr. Bernhard Nebel nebel@informatik.uni-freiburg.de joined Univ. of Freiburg Stephan Pfab spf@pc-plus.de Dr. Harald ruess@csl.sri.com joined SRI International, Menlo Park, CA Dr. Jussi Rintanen rintanen@informatik.uni-freiburg.de joined Univ. of Freiburg Detlef Schwier detlef@blaxxun.de joined blaxxun interactive, München Dr. Martin Strecker Martin.Strecker@in.tum.de joined TU München Dirk Tyschler Dirk.Tyschler@gmx.net joined Bayer AG, Leverkusen Petra Tyschler Petra.Tyschler@gmx.net joined Allianz AG, Stuttgart Prof. Dr. Adelinde
Citation
ACM Transactions on Programming Languages and Systems (TOPLAS) archive Volume 16, Issue 3 (May 1994) toc The temporal logic of actions Author Leslie Lamport
http://portal.acm.org/citation.cfm?id=177726&dl=ACM&coll=portal&CFID=11111111&CF
Results
Search Results. Nothing Found. Your search for temporal logic IN CCS did notreturn any results. temporal logic CCS Advanced Search Search Help/Tips.
http://portal.acm.org/results.cfm?query=Temporal logic CCS&coll=portal&dl=A
Temporal Logic In Specification 1987
dblp.unitrier.de temporal logic in Specification 1987 Altrincham, UK. 1-20;Shmuel Katz, Doron Peled Interleaving Set temporal logic.
http://www.informatik.uni-trier.de/~ley/db/conf/tls/tls1987.html

Extractions: Behnam Banieqbal Howard Barringer Amir Pnueli (Eds.): Temporal Logic in Specification, Altrinchamm UK, April 8-10, 1987, Proceedings. Lecture Notes in Computer Science 398 Springer 1989, ISBN 3-540-51803-7 DBLP Pierre Wolper : On the Relation of Programs and Computations to Models of Temporal Logic. 75-123 Zohar Manna Amir Pnueli : Specification and Verification of Concurrent Programs by forall-Automata. 124-164 Bernhard Josko : MCTL - An Extension of CTL for Modular Verification of Concurrent Systems. 165-187 Edmund M. Clarke Orna Grumberg : The Model Checking Problem for Concurrent Systems with Many Similar Processes. 188-201 Moshe Y. Vardi
International Conference On Temporal Logic 1994
Dov M. Gabbay, Hans Jürgen Ohlbach (Eds.) temporal logic, First InternationalConference, ICTL '94, Bonn, Germany, July 1114, 1994, Proceedings.
http://www.informatik.uni-trier.de/~ley/db/conf/ictl/ictl1994.html

Extractions: Dov M. Gabbay (Eds.): Temporal Logic, First International Conference, ICTL '94, Bonn, Germany, July 11-14, 1994, Proceedings. Lecture Notes in Computer Science 827 Springer 1994, ISBN 3-540-58241-X DBLP Odd Erik Hansen : Combining Temporal Specification Techniques. 1-16 Shmuel Katz : Global Equivalence Proofs for ISTL. 17-29 Jos C. M. Baeten Jan A. Bergstra Roland N. Bol : A Real Time Process Logic. 30-47 T. S. E. Maibaum : Sometimes "Tomorrow" is "Sometime" - Action Refinement in a Temporal Logic of Objects. 48-66 Anthony J. Bonner Michael Kifer : Applications of Transaction Logic to Knowledge Representation. 67-81 Patrick Doherty Witold Lukaszewicz : Cicumscribing Features and Fluents. 82-100 Silvana Badaloni Marina Berati : Dealing with Time Granularity in a Temporal Planning System. 101-116 M. Reynolds : Axiomatizing U and S over Integer Time. 117-132 Valentin Goranko : Temporal Logic with Reference Pointers. 133-148 Yde Venema : Completeness through Flatness in Two-Dimensional Temporal Logic. 149-164 Bart Vergauwen Johan Lewi I. Avau
The Temporal Logic Of Actions
A logic for specifying and reasoning about concurrent systems.
http://www.research.digital.com/SRC/tla/
Temporal Logic From FOLDOC
temporal logic. logic An extension There are two types of temporal logicused branching time and linear time. The basic propositional
http://wombat.doc.ic.ac.uk/foldoc/foldoc.cgi?temporal logic
SRI International - Computer Science Laboratory - Ground Temporal Logic: A Logic
A temporal logic designed to specify properties of hardware at the register transfer level.
http://www.csl.sri.com/reports/html/cav94.html

Extractions: Abstract: We present a new temporal logic, GTL, appropriate for specifying properties of hardware at the register transfer level. We argue that this logic represents an improvement over model checking for some natural hardware verification problems. We show that the validity problem for this logic is Pi 1-1 complete. We then identify a fragment of the logic that is decidable. We show that in this fragment we are still able to encode many interesting problems, including the correctness of pipelined microprocessors. BibT E X entry:
No Match For Linear Temporal Logic
No match for Linear temporal logic. Sorry, the term Linear temporal logicis not in the dictionary. Check the spelling and try removing
http://wombat.doc.ic.ac.uk/foldoc/foldoc.cgi?Linear Temporal Logic

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