Product Description
The Designer's Guide to Verilog-AMS presents Verilog-AMS, the new analog and mixed-signal extensions to the widely used Verilog hardware description language.
It starts by describing a rigorous and proven top-down design methodology. Top-down design is widely seen as the key to being able to design very large and complex mixed-signal circuits and it is enabled by Verilog-AMS. Verilog-A and Verilog-AMS are then introduced without assuming that the reader has a background in behavioral modeling. Finally, it includes a comprehensive reference guide for the language.
The Designer's Guide to Verilog-AMS is extensively cross-referenced and indexed, making it an ideal reference for both Verilog-A and Verilog-AMS. A companion website, www.designers-guide.com, provides electronic copies of all the models used in this book, a library of user-contributed models, a discussion forum, additional documents on simulation and modeling, and other useful material.
The Designer's Guide to Verilog-AMS is written for analog and mixed-signal designers, particularly those designing larger and more complex circuits. ... Read more

Customer Reviews (5)

It's pretty good, actually
This book has no competition that I know of. There are no other books about Verilog-AMS so no relative comparison is possible. But I admit that I do not regret spending the money for my copy, and until something better comes along, you should too if you are expecting to do any work in Verilog-AMS.

Note that this is not a text book in Analog/Mixed signal simulation in general. People planning to get this book really should know the generic basics already.

Verilog AMS
I design ADCs. I bought this book because we the tool became available to me at work. My first impression was underwhelming. However, as a reference book I have found it useful, and one of my associates borrows it also.

This is about all that is available. It is useful.

An introduction to Verilog AMS
I am new to verilog A and even newer to Verilog AMS.I thought the book was a reasonable introduction to the language, but I prefer a longer text with more content.The book is only of moderate length and expensive as seems to be typical of Kluwer texts.There are also some spots where clarity, at least to myself, was lacking.A user will need the Verilog AMS license from Cadence to use this language.Lacking such a license, I was never able to apply the mixed signal info from the text.For the pure Verilog A user who is doing only analog and not mixed signal sims, this book may not offer an advantage over Fitzpatrick's book even though it is newer.For the practicing engineer, this text is a far better way of getting introduced to Verilog AMS than Cadence's cryptic documentation.

Excellent introduction to the language & excelent reference
This book is currently the only up-to-date reference book for Verilog-A and Verilog-AMS (the book by Fitzpatrick is very incomplete and way out of date).

It introduces the language by using a series of relatively simple yet useful examples. In doing so it gets you up and running quickly and then builds your knowledge of the language. It takes you through Verilog-A in some depth, then presents enough Verilog-HDL (the digital subset) to give analog designers a workable understanding of Verilog, and then covers Verilog-AMS in depth.

The book has one chapter that acts as a complete reference for the manual for VerilogA/MS and and excellent index. I use the book as a reference as I write models and can always find what I am looking for very quickly.

In short, I recommend it whole-heartily. It is an essential book for anyone that uses Verilog-A or Verilog-AMS.

-August

Pointer to more information
I am one of the authors of this book and I wanted to let you know that if you wished to find out more about it before your ordered it, you can go to its home page, which can be found at http://www.designers-guide.com/Books/. It contains considerably more information about the book, including excerpts.

Amazon would not allow me to post this message to you without giving the book a star rating. So I did my best to provide an unbiased opinion ;-).

-Ken ... Read more

Product Description
Revised and updated in accordance with the new 1364-2001 standard, much of which applies to synthesizable Verilog. Over 100 runable examples included on the CD-ROM. ... Read more

Customer Reviews (5)

Excellent book
An excellent book for those who already understand programming and digital electronics. However, failure in some examples that could be more detailed.

I recommend to all who understand electronics and are programmers.

-----------

Um excelente livro para quem já programa e entende de eletrônica digital. Porém, falha em alguns exemplos que poderiam ser mais detalhados.

Recomendo para todos os que entendem eletrônica e são programadores.

easy transition to verilog, good reference book
I have a VHDL background and this book was recommended to me. It made a smoooth transition into verilog. I read the book globally and then kept the book as a reference on my desk. If I needed something specific like file I/O and generating vectors, I used the example as a template to complete my verification. Also it helped to organize my files, like having one verification environment and easily plugging in tests by use of common tasks. Currently I am using Verilog and System Verilog, this book is still used regularly.

Save your money
This is a typical Verilog book, which isn't saying much. The examples tend to be contrived and mostly show how *not* to write good Verilog code - by the author's own admission! You won't find a decent example of how to model a flip flop until pg. 144, in the chapter "Advanced Procedural Modeling." If you really want this book anyway, buy it used and keep it for reference.After all, in the introduction the book says "Some of the information you want might be outside the scope of this book. Some of the other sources are simulator reference manuals; and the comp.lang.verilog usenet news group." (sic)

You could also try "HDL Chip Design" by Smith since it covers Verilog and VHDL.At least it shows good style and thoroughly explains what each line of code is doing and shows synthesis results with small schematics.

Very good book for beginer
I was lucky to have James Lee class at ucsc/ca. This book will
be very useful for all reader from beginer to practical expert.

Verilog testbench reference
The book provides a good resource for those designers that already know Verilog and wish to have coding tips for simulation testbenches.

It is learn-by-example format, and is updated to include the '99 verilog standard. The book is well laid out, meaning that from the index it is easy to find a relevant coding example.

I also bought "A designers guide to VHDL" Peter J. Ashendon which is a language reference for VHDL by example. ... Read more

Product Description
Contributions on UML address the application of UML in the specification of embedded HW/SW systems. C-Based System Design embraces the modeling of operating systems, modeling with different models of computation, generation of test patterns, and experiences from case studies with SystemC. Analog and Mixed-Signal Systems covers rules for solving general modeling problems in VHDL-AMS, modeling of multi-nature systems, synthesis, and modeling of Mixed-Signal Systems with SystemC. Languages for formal methods are addressed by contributions on formal specification and refinement of hybrid, embedded and real-time stems.
Together with articles on new languages such as SystemVerilog and Software Engineering in Automotive Systems the contributions selected for this book embrace all aspects of languages and models for specification, design, modeling and verification of systems. Therefore, the book gives an excellent overview of the actual state-of-the-art and the latest research results. ... Read more

Product Description

Verification is increasingly complex, and SystemVerilog is one of the languages that the verification community is turning to. However, no language by itself can guarantee success without proper techniques. Object-oriented programming (OOP), with its focus on managing complexity, is ideally suited to this task.

With this handbook—the first to focus on applying OOP to SystemVerilog—we’ll show how to manage complexity by using layers of abstraction and base classes. By adapting these techniques, you will write more "reasonable" code, and build efficient and reusable verification components.

Both a learning tool and a reference, this handbook contains hundreds of real-world code snippets and three professional verification-system examples. You can copy and paste from these examples, which are all based on an open-source, vendor-neutral framework (with code freely available at www.trusster.com).

Learn about OOP techniques such as these:

• Creating classes—code interfaces, factory functions, reuse
• Connecting classes—pointers, inheritance, channels
• Using "correct by construction"—strong typing, base classes
• Packaging it up—singletons, static methods, packages

Product Description

This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project.

In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs.

Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided on the accompanying CD-ROM. For a reader with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book.

A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back-annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test.

Coverage of specific devices includes basic discussion and exercises on flip-flops, latches, combinational logic, muxes, counters, shift-registers, decoders, state machines, memories (including parity and ECC), FIFOs, and PLLs. Verilog specify blocks, with their path delays and timing checks, also are covered.

Customer Reviews (1)

nice way to learn Verilog
Verilog is one of the key languages for chip layout. Not especially difficult, but you still have to somehow learn it. You can easily get manuals on Verilog, but those aren't well suited as a learning pedagogy. The attraction of this book is that it lays out [pun intended] just such a learning path. The chapters explain various aspects of the language. In toto, you get a pretty exposure to most of the language.

Plus, Verilog allows powerful simulations of chips. Necessary to reduce the cost of actually fabricating a functioning design. Another advantage of the book is that you learn how to use Verilog for design for testing, and for doing that testing. ... Read more

Product Description
Analog Behavioral Modeling With The Verilog-A Languageprovides the IC designer with an introduction to the methodologies anduses of analog behavioral modeling with the Verilog-A language. Indoing so, an overview of Verilog-A language constructs as well asapplications using the language are presented. In addition, the bookis accompanied by the Verilog-A Explorer IDE (Integrated DevelopmentEnvironment), a limited capability Verilog-A enhanced SPICE simulatorfor further learning and experimentation with the Verilog-A language.This book assumes a basic level of understanding of the usage ofSPICE-based analog simulation and the Verilog HDL language, althoughany programming language background and a little determination shouldsuffice. From the Foreword: `Verilog-A is a new hardware design language (HDL) for analogcircuit and systems design. Since the mid-eighties, Verilog HDL hasbeen used extensively in the design and verification of digitalsystems. However, there have been no analogous high-level languagesavailable for analog and mixed-signal circuits and systems. Verilog-A provides a new dimension of design and simulation capabilityfor analog electronic systems. Previously, analog simulation has beenbased upon the SPICE circuit simulator or some derivative of it.Digital simulation is primarily performed with a hardware descriptionlanguage such as Verilog, which is popular since it is easy to learnand use. Making Verilog more worthwhile is the fact that several toolsexist in the industry that complement and extend Verilog'scapabilities ... Behavioral Modeling With the Verilog-A Language provides a goodintroduction and starting place for students and practicing engineerswith interest in understanding this new level of simulationtechnology. This book contains numerous examples that enhance the textmaterial and provide a helpful learning tool for the reader. The textand the simulation program included can be used for individual studyor in a classroom environment ...' Dr. Thomas A. DeMassa, Professor of Engineering, Arizona StateUniversity ... Read more

Customer Reviews (3)

Riddled with errors
This book definately need an editor. Many of the examples,even the basic examples are riddled with errors. It is an ok read but don't expect to be a novice after reading this book.

followup on prior review
the book introduces the methodology to analog behavioral modeling - starting with basics andthen introducing complex examples (in the biggest chapter).the examples include an opamp and characterization of it.maybethe other reviewer did not get that far.a valid drawback is that the mostrecent specification for Verilog-A/Verilog-AMS has changed sincepublication (most constructs are still valid though).

It provides little information about Verilog-A
This book is the only one that I can find in the bookshelf discuss Verilog-A language. I expect it can provide some examples to model a real world analog circuit using Verilog-A language, but I am disappointedbecause this book provides only simple description about resistors,capacitors, etc. You can't even find how to model an opamp in this book. ... Read more

Product Description
The Verilog hardware description language provides the abilityto describe digital and analog systems for design concepts andimplementation. It was developed originally at Gateway Design andimplemented there. Now it is an open standard of IEEE and Open VerilogInternational and is supported by many tools and processes. TheComplete Verilog Book introduces the language and describes itin a comprehensive manner. In The Complete Verilog Book, each feature of the language isdescribed using semantic introduction, syntax and examples. A chapteron semantics explains the basic concepts and algorithms that form thebasis of every evaluation and every sequence of evaluations thatultimately provides the meaning or full semantics of the language.The Complete Verilog Book takes the approach that Verilog is notonly a simulation language or a synthesis language or a formal methodof describing design, but is a totality of all these and covers manyaspects not covered before but which are essential parts of any designprocess using Verilog. The Complete Verilog Book starts with atutorial introduction. It explains the data types in Verilog HDL, asthe object-oriented world knows that the language-constructs and datatypes are equally important parts of a language. The CompleteVerilog Book explains the three views, behavioral, RTL andstructural and then describes features in each of these views. The Complete Verilog Book keeps the reader abreast of currentdevelopments in the Verilog world such as Verilog-A, cycle simulation,SD, and DCL, and uses IEEE 1364 syntax. The Complete Verilog Book will be useful to all those who wantto learn Verilog HDL and to explore its various facets. ... Read more

Customer Reviews (3)

Good book, high price!
I liked the approach of describing the gate model, dataflow and behavioral model, all in one place, unlike other books. The text is mostly very clear.More state diagrams here and there may clarify. Unfortunatly PLI is not really covered. The CD rom contains only the code: other books provide a free (student version) vhdl simulator. At $ 135.00 + tax, the price is high, compared to other similar books covering the same topic.

A.G.- San Jose, CA

Good reference mediocre for learning.
The book has plenty of code samples, however, many of them have mistakes, making it difficult and sometimes frustrating to study the code.The explanations are not well written when compared to other books (Thomas andMoorby's), however there is some information that cannot be found in otherbooks.An excellent book except for the price and mistakes on nearly everypage.If you are already experienced in Verilog, this may be an excellentreference, however, if you are just learning, Thomas Moorby's "TheVerilog Hardware Description Language" is an excellent and highlyrecommended book.

a great book with almost everything for designers to referen
This book is really a worthwhile book to read and study for advanced topics of designs based on Verilog and Synopsys synthesis tools.The feature-rich topics and details of how the constructs of the designs aremade are quite clear and well-written for people involved.The only thingI'm concerned is the price seems to be way way too high to general reader,as it's $135 before tax.Hopefully the price can drop at least 40% less sothat everybody can buy it.regards,JKL, San Jose, Calif. ... Read more

Product Description
The art of transforming a circuit idea into a chip has changed permanently. Formerly, the electrical, physical and geometrical tasks were predominant. Later, mainly net lists of gates had to be constructed. Nowadays, hardware description languages (HDL) similar to programming languages are central to digital circuit design. HDL-based design is the main subject of this book.
After emphasizing the economic importance of chip design as a key technology, the book deals with VLSI design (Very Large Scale Integration), the design of modern RISC processors, the hardware description language VERILOG, and typical modeling techniques. Numerous examples as well as a VERILOG training simulator are included on a disk. ... Read more

Product Description
Intended for an introductory course in digital logic design. The authors provide a balance between classical and modern design approaches. Basic concepts are introduced using simple log circuits, which are designed by using both manual techniques and modern CAD-tool-based methods. ... Read more

Customer Reviews (3)

Very Good but late arrival
THe book was in excellent condition but the only flaw was that it arrived after 20 days...very slow service...go to some other sellers...avoid these people...!!!

2nd unrevised edition
The publishers have just reprinted the book, with new page breaks. The only addition that I can see are solutions to select problems, tacked on at the very end. Get a used copy, save some money, and buy other good books out there!

Good deal
Faster than expected delivery and still in decent condition.Even has cd though outdated.Overall, very satisfied. ... Read more

Customer Reviews (21)

A good book to learn Verilog and VHDL at once
This book places Verilog and VHDL code side by side and makes learning both languages simultaneously easy.It also shows the synthesized the circuits.It is easy to lose sight of the logic circuits that the HDL tries to describe, especially for people whose background is not electrical.This book brings circuit reality back from the HDL abstraction.

The book binding is not good; the book falls a part easily.Mine has to go in a binder now.

HDL Chip Design
An excellent reference book and in remarkably good condition. I ordered this book and VHDL by Douglas L. Perry and both arrived in less than a week. I am very pleased with this transaction.

The first book that made HDL clear to me
This book contains examples of code in Verilog, VHDL, AND C!The value of this was to build my understanding of what the HDL is doing.Although it reads like a "cookbook" the 'recipes' clearly compare the ways a recipe can be cooked.I recommend this as both a learning tool and as a reference.

Includes essential coverage for both Verilog and VHDL
The book nicely covers both Veriloh and VHDL in general. However, it doesn't cover any of them deeply. It is essentially a good book for engineers who have background and knowledge in one of the HDLs and need to get familiar with the other one as it has sufficient examples and code comparisons.However, it is not an advanced book in either Verilog or VHDL. For example, it doesn't cover compiler directive commands or transistor level modeling in Verilog. It doesn't compare and analyze the synthesis results of different coding styles and different optimization approaches either.Unfortunately, the indexing of the book is very poor and doesn't help you if you need to find something quickly.

Overall, this is a good book to have if you need to switch between Verilog and VHDL and need to compare and grab fundamental concepts.

Unique coverage of both Verilog and VHDL
This book is a unique text on several levels, providing information rarely found in most academic treatments of the subject targeted at beginning students.

It covers and compares VHDL and Verilog impartially, describing their differences, strengths and weaknesses.

It has side by side VHDL and Verilog code - if you know one language, this is an excellent reference to the other language.My copy of the book was used by several engineers to cross train themselves in Verilog or VHDL.

Code is given for practical, real world circuits.From multiplexers to FSM to ALU, it is all in there.Each "class" of circuit is given its own chapter and covered in depth.The FSM chapter is 74 pages, for example.

There are many illustrations of the resulting synthesized logic.A picture is worth a thousand words, and seeing the result of different coding styles is very instructive.For example, coded one way, you get asynchronous resets, coded another, you get synchronous set/reset on your flipflops.

Beyond just a cookbook of VHDL and Verilog reference code, the book does cover such topics as scan test structures, simulation, hierarchial design, but these topics do not receive an in-depth coveraqe.There is an entire chapter dedicated to writing test harnesses, again with side-by-side code for VHDL and Verilog.

My copy saw use in multiple real world projects, by multiple, experienced engineers.It was most often used by VHDL (or Verilog) experts to learn Verilog (or VHDL).It was also used as a reference for coding particular structures.Quickly providing the answer to questions like "how do I code a carry lookahead in Verilog?"Eventually, I had to stop loaning it out as the pages began to fall out from the high volume of use.Unfortunately, it is no longer in print, so I have to use it very carefully, and coworkers are forced to struggle with inferior texts for reference.

... Read more

Product Description
The first edition of Principles of Verifiable RTL Design offered acommon sense method for simplifying and unifying assertionspecification by creating a set of predefined specification modulesthat could be instantiated within the designer's RTL. Since therelease of the first edition, an entire industry-wide initiative forassertion specification has emerged based on ideas presented in thefirst edition. This initiative, known as the Open Verification LibraryInitiative, provides an assertion interface standard that enables thedesign engineer to capture many interesting properties of the designand precludes the need to introduce new HDL constructs (i.e.,extensions to Verilog are not required).Furthermore, this standardenables the design engineer to `specify once,' then target the sameRTL assertion specification over multiple verification processes, suchas traditional simulation, semi-formal and formal verificationtools. The Open Verification Library Initiative is an empoweringtechnology that will benefit design and verification engineers whileproviding unity to the EDA community (e.g., providers of testbenchgeneration tools, traditional simulators, commercial assertionchecking support tools, symbolic simulation, and semi-formal andformal verification tools).The second edition of Principles ofVerifiable RTL Design expands the discussion of assertionspecification by including a new chapter entitled `Coverage, Eventsand Assertions'. All assertions exampled are aligned with the OpenVerification Library Initiative proposed standard. Furthermore, thesecond edition provides expanded discussions on the following topics:+ start-up verification; + the place for 4-state simulation; + raceconditions; + RTL-style-synthesizable RTL (unambiguous mapping togates); + more `bad stuff'.The goal of the second edition is to keepthe topic current. Principles of Verifiable RTL Design, A FunctionalCoding Style Supporting Verification Processes, Second Edition tellsyou how you can write Verilog to describe chip designs at the RTLlevel in a manner that cooperates with verification processes. Thiscooperation can return an order of magnitude improvement inperformance and capacity from tools such as simulation and equivalencecheckers. It reduces the labor costs of coverage and formal modelchecking by facilitating communication between the design engineer andthe verification engineer. It also orients the RTL style to providemore useful results from the overall verification process. ... Read more

Customer Reviews (3)

has practical tips, is shallow in giving understanding
The chapter on bad stuff is useful and practical, even though it repeats parts of previous chapters. The chapter on assertion based verification is practical too. Some of the reasonings on use of "x" may be debatable. For example, the authors argued that two-state detects more problems than x injection, based on their experiences. In the text, an example was given. What the example illustrates is NOT the inherent problems with x injection but a truly bad style of coding to detect x. Thus, the example is misleading.

The chapter on formal verification is a cheat-sheet user manual for some commercial tools. It gives a couple of lines of math symbols about formal verification theory, without explanation whatsoever. In general, this chapter is too shallow for understanding the ideas behind formal verification.

In many places, the book just lists the benefits of some practices without giving reasons and details about the practices. It's very frustrating to have the thought hung in mid-air.

So if you are looking for a partial collection of tips to avoid simulation based verification problems, this book is a start. If you want a more in-depth and complete understanding in verifiable RTL design, find other books.

An excellent book for advanced users
This book presents principles drawn from very large scale designs, like microprocessor.If you are looking for a book describing testbench implementation, another book, "Writing testbenches functional verification of hdl models", is more suitable.If you are working on very large scale and complex design verification, this book will be very helpful.The discussion of simulation optimization, X/Z state, X/Zero/Random initialization during simulation is very insightful.

Out of the ordinary
If you are looking for another book describing the Verilog Language Reference Manual then this book is not for you.If, however, to are looking for an excellent set of principles to build a design andverification philosophy then I highly recommend this book.The authorshave produced an RTL centric view of design emphasizing the verificationprocess. They argue that synthesis productivity gains have now placed theverification process in the critical path and that equal attention shouldbe giving to coding for verification as is currently given to coding forsynthesis.The chapter I particularly enjoyed, entitled "BadStuff," provides an excellent discussion with examples on codingstyles that hinder efficient verification. The author's discussion of theproblems with the use of X at the RT-level, due to X-state pessimism andoptimism, and the need for 2-state RTL simulation is enlightening. ... Read more

Product Description
Guides you through every key challenge associated with designing FPGAs and ASICs using Verilog, one of the world's leading hardware design languages. Provides rigorous coverage of what it really takes to translate HDL code into hardware-and how to avoid the pitfalls that can occur along the way. CD-ROM included. DLC: Field programmable gate arrays--CAD. ... Read more

Customer Reviews (12)

The Book's Title fits
Ken's book contains many helpfull hints for the day to day FPGA design. It explains very well the pitfalls you will be trapped by and answers e.g. questions like what is actually is the difference between blocking and non-blocking assignment.

Sloppy and incoherent, some useful information
This book addresses how to use Verilog to create working FPGA designs. It touches on topics such as clocking, implementation of specific types of logic blocks, and design flow. The examples are written using Verilog.

The writing is sloppy, the organization is incoherent, and the explanations are incomplete. A reader may find the book worthwhile if: he or she already knows most of the material presented, has a few problems that are addressed by the book, can find the discussion of that problem in the book, and the discussion is one of those that is complete and accurate. Otherwise, the book is a waste of time and money.

The author assumes that the reader is familiar with digital logic design, the basics of Verilog, and the basics of FPGA and ASIC design. The book discusses strategies for dealing with practical problems. Unfortunately, the strategies are presented in a disorganized manner, with explanations that are poorly thought out and too incomplete to use.

The first chapter introduces Verilog design for FPGA synthesis. The contents of the chapter are a mish-mash. It is hard to tell what you are supposed to know after reading the chapter that you didn't have to know before reading it. The chapter isn't a quick description of Verilog, because it leaves out most Verilog syntax that you have to know (for example, vectors). The chapter isn't limited to describing what subset of Verilog is synthesizable, because it has detailed but incomplete descriptions of random Verilog topics such as number formats (eg. 1'b0). There are even pages of tables showing boolean logic truth tables for basic logic primitives such as and, or, and xor.

The second chapter is a discussion of how FPGAs are implemented, and the effect that this has on synthesis. For example, clocking strategies are discussed, with some references to differences between FPGAs and ASICs. There is also a discussion of how a logic synthesizer might operate. A few other topics are thrown in, such as a discussion of DeMorgan's theorems. The chapter is too incomplete and poorly-written to be of much practical use. For example, although there is a description of how logic elements can be built out of transistors (including simplified schematics of one possible approach), there is no serious discussion of what implications this has. The book is about FPGA design, but the section on how logic functions are implemented in most FPGAs (as lookup tables) does not describe this in any detail.

The third and fourth chapters, regarding implementing specific digital circuits in FPGAs using Verilog, are potentially the most useful. The concept of the chapters is that they show how to write Verilog for useful functions in a way that can be synthesized well into FPGAs. If the chapters had been well organized and complete, the book would have been worth buying just for them. However, the chapters are as poorly-written as the rest of the book. Large sections are taken up with a discussion of writing adders and subtractors - showing that there is little point in doing so yourself instead of letting the synthesizer do it. However, the discussion of finite state machines - an important topic - covers state machines implemented using binary or Gray codes to represent states. The discussion of 'one-hot' state machines (frequently used in practice in FPGAs) is incomplete, describing only the problems, but failing to present an example that works (or any example at all). Similarly, the discussion of FIFOs (important to synchronize portions of large designs) is limited to a few notes about problems, without a single example. This is surprising, because the book emphasizes that the designer must solve clocking and synchronization problems across large designs, yet solutions to this problem (such as FIFOs) are not described.

The second half of the book, mainly chapters 5 through 8, describe how to use specific Verilog tools. The chapters are useless reiterations of documentation for obsolete versions of specific tools.

Chapter 9, the last chapter, is about designing for ASIC conversion. This could have been a useful chapter, because it covers an important topic.

All in all, I think this is a book to avoid.

On the positive side, this book seems to have fewer obvious editing errors than most other 'instant books'. Also, the typesetting is fairly normal, with reasonable sized text and reasonable margins. The organization and contents of the section headings is hard to understand, but that is a reflection of the disorganization of the book, rather than a problem with the design. The only significant problem I had with the graphic design of the book relates to the graphics, primarily schematics with some screen captures. The scaling is not uniform, so in a single explanation, the size of a schematic symbol and associated label might vary from graphic to graphic. However, this is a minor problem.

It scratched my itch....
This book fit nicely in the gap I noticed between books on digital design with Verilog that were written from a structured academic standpoint and product specific user manuals and application notes.To learn effective FPGA design from books one would desire to have this book along with the other two; lacking "Real World FPGA Design" one would have to ask colleagues lots of questions and learn the rest the hard way.

I am using this book as I 'retool' as a FPGA Digital Design Engineer since full-custom design jobs here are drying up since few companies can afford the investment of time and money to bring custom devices to market.I wish there was a book like this for the classic chip design world that I could wave at the newbie system and digital designers that wanted me to add an 8 input NOR gate to the library that could drive a fanout of 50 loads 10 mm away.

Verilog is a many-faceted gem; I have been using it since the early 90's, albeit at the switch and structural level.This book is useful to me as I learn to design in Verilog at greater level of abstraction and it differs from other texts I have found in that it does not lose sight of the lower-level 'gotchas'.

The only thing that keeps me from giving this book my highest rating is that there are some errors that do need correcting;the URL listed in another review here remedies that problem.

Good writing style
I'm an analog design engineer with over 20 years of experience in industry.I want to add FPGA's to my bag of tricks, and I ran across Mr. Coffman's book via a search with Google.My book arrived a week ago and I am finding it to be just the kind of book I have been looking for.He has a good writing style, very easy to follow.I plan to invest many hours working through his examples with the included software.I have read other reviews of this book at this Amazon site.Some people are looking for an academic book on Verilog.Others are looking for a book that will teach them Verilog without spending the time programming and simulating (ie learning without doing homework).If you fall into either of these groups, this book is not for you.However, if you are an experienced engineer looking to learn about Verilog and VHDL through honest study and experimenting, then Mr. Coffman's book is an excellent choice to guide you through this process with a focus on the "real world".You also may find yourself chuckling at some of his commentary on the way

Excellent jump-start book for engineers!
Anyone who understands C/pascal is going to love Ken's book.It's the perfect reference to sit next to your keyboard for a quick hands-on reference!

Ken taught me in 1 minute how to create an array of cells in an FPGA simply via the TOC!In another minute I was implementing static-keys into a ROM'd lookup table.

It could not have been easier.

*Anyone trying to implement algorithms in Verilog should by this book* ... Read more

Product Description
Written for new users.

Explains the language through simple examples.

Explains the syntax of language using commonly-used design terminology.

Explains the behavioral style, the dataflow style, and structuralstyle in detail.

Concepts of delay and timing are clearly explained.

Testbench writing is made easier by providing a number of examples.

Many hardware modeling examples have also been provided to make thisan excellent reference. ... Read more

Customer Reviews (7)

A little disappointed
With such a high rating, I had hoped for something better.

If you are looking for a very introductory lesson on the workings of Verilog, this is for you. However if you are looking for something that will help you learn to write complex code, this is not it.

My biggest complaint is that this book needs to be hit pretty hard by an editor who actually understands Verilog enough to find the syntax errors and omissions in the example code. If this is supposed to be a "primer" all of the examples should be technically and syntactically correct, and they are not. I am able to find mistakes and this is my first foray into Verilog.

Also note: this does not teach anything about synthesizable code. That's another book, but the difference is never even mentioned.Almost everything in this book will help you learn how to write test benches for you synthesizable modules.

Not a very good book
Occasionally you see books that seem to be compiled by the author's lecture notes, this is one of them. It would still be ok if the notes were good, however this one isn't. It does it's job presenting the basics of Verilog, but on harder to understand concepts such as blocking/non-blocking procedural assignments and procedural continuous assignment, the author does an aweful job explaining it, which is where it counts the most. Similar problems appear throughout the book, and I can never understand why it has attained a four star rating, which is when I purchased it. If you can find a better book, go for it!

A must have book
While some might say that it's a beginners' book, you will
end up using this book the most. I have several Verilog
books in my cube at my work, but this is the book my
colleagues come very often to look up. This has excellent
and authentic descriptions of all Verilog language rules
and primitives. It also explains how and when to use
different Verilog constructs. I bet you will not regret
having this book.

Regurgitation of LRM
This book is basically a regurgitation of the language reference manual and really does not give the reader any insight into when and how to use particular language constructs. For example on page 148 the author discusses module ports and has an example of a port redeclaration, but he neglects to discuss why you would wish to redeclare a port as a wire. If you are learning Verilog because you are going to use it in an actual design look elsewhere.

Well Organised
This book is well organized.All the chapters are thoroughly written and hence easily understood by a beginner.I would personally refer this book both fora beginner and a practicing engineer. ... Read more

Product Description
Principles of Verilog PLI is a `how to do' text onVerilog Programming Language Interface. The primary focus of the bookis on how to use PLI for problem solving. Both PLI 1.0 and PLI 2.0 arecovered. Particular emphasis has been put on adopting a genericstep-by-step approach to create a fully functional PLI code. Numerousexamples were carefully selected so that a variety of problems can besolved through ther use. A separate chapter on Bus Functional Model(BFM), one of the most widely used commercial applications of PLI, isincluded. Principles of Verilog PLI is written for the professionalengineer who uses Verilog for ASIC design and verification. Principles of Verilog PLI will be also of interest to studentswho are learning Verilog. ... Read more

Customer Reviews (5)

Multiple instances of same module containing a PLI call
Swapnajit, First congratulations on your book. This is a major progress in documenting and demistifying the PLI mechanism. The examples of your bookare excelent starting points.I grade myself as a medium expert in PLI. SoI am still waiting for a second, higher-class book to cover more advancedtopics. One of them is multiple instances of a module containing a PLI calland hence multiple instances of the same Ccode. My problems started whendata belonging to one instance interfered with data belonging to otherinstance. Actually I would like to see in your next book or revision sometips about this issue. In general some good PLI coding practices would bewellcomed. I also encountered race conditions in which the order of the PLIC routines calling influenced the behaviour, and hence not reliable.Thesecond subject I liked very much in your book is the communication betweenverilog processes. The actual application I hoped to be able to put to workis a kind of "software -hardware coverification" (for poors).Actually I have a PLI that mimics the bus activity of a CPU and now I wantit to run real C program. I would like that C program to run in a differentenvironment from the simulator, and only on CPU-read and CPU-write toenable a handshake mechanism. Since I am not a TCP IP socket expert Idropped the effort after a couple of days, when I reached the notoriousdeadlock of both processes waiting for one another... I would also like tosee in the next revision tips about debugging, and some NOT-TO-DOs. Iencountered some problems when using parameters in verilog that are passedalso to PLI's. I think you may add some words about this as well. All inall I enjoyed the book. Keep up ! Last but not least thank you for youranswers to my e-mails regarding the PLI stuff. I also appreciate youractivity in the comp.lang.verilog forum.

Fair at best.Other books are better.
Save your money and buy the Stuart Sutherland book "The Verilog PLI Handbook"ISBN 0-7923-8489-X it's much better.I have both.

Essential for anybody seeking to learn Verilog PLI
Absolutely essential for anybody seeking to learn the fundamentals of Verilog PLI. Various usagesof Verilog PLI including different types of library functions :access and utility routines as well as VPIs areextensively covered with numerous detailed examples. The reviewer found thebook to be a well read and lucidly written.

A very useful book
This is a very useful book for those who want to learn intricacies of Verilog PLI without spending hours on reading manuals. The best part of this book that I liked is its set of examples - almost all functions andtheir uses have been explained with an easy-to-understand example. Most ofthese examples are presented in their bare-bone structure so that users cancustomize them according to their needs. A more careful look at theexamples would reveal that the author has subtly divided them into twocategories - one for the beginners and the other for the more advancedusers.

Overall, I will recommend this book to anybody who wants to learnVerilog PLI.

Excellent book!
I found the book very useful because of the lots of examples, informal presentation(helps beginners), seperate chapter on BFM, coverage for both PLI1.0 and PLI2.0 and exercise (Self-check) to measure progress.

I am ofthe opinion that this book would be a worthy investment for a quick startin hardware design. ... Read more

Product Description
Verilog HDL is the standard hardware description language for the design of digital systems and VLSI devices. This volume shows designers how to describe pieces of hardware functionally in Verilog using a top-down design approach, which is illustrated with a number of large design examples. The work is organized to present material in a progressive manner, beginning with an introduction to Verilog HDL and ending with a complete example of the modelling and testing of a large subsystem. ... Read more

Product Description
Provides a practical approach to Verilog design and problem solving.
* Bulk of the book deals with practical design problems that design engineers solve on a daily basis.
* Includes over 90 design examples.
* There are 3 full scale design examples that include specification, architectural definition, micro-architectural definition, RTL coding, testbench coding and verification.
* Book is suitable for use as a textbook in EE departments that have VLSI courses ... Read more

Customer Reviews (3)

Sparse Index
This is a 309-page book with a one and a half page index! I can't count how many times I have pulled out this book, looked for a particular topic in its index, and put the book back on the shelf.

Not obvious from the title, although Lee says so on the back cover, this book describes a design flow for ASIC design. That makes me wonder if there exists a Verilog book that describes a design flow for microprocessor design.

A reasonable introduction to Verilog is provided on the CD accompanying "Computer Organization and Design: The Hardware/Software Interface", Third Edition. [...]

For an HDL-independent explanation of register-transfer-level (RTL) and behavioral modeling, I really like Figure 1-1 in "The Designer's Guide to VHDL" and its accompanying text, although Peter Ashendon gives credit to Gajski and Kuhn ("New VLSI Tools", IEEE Computer, Vol. 16, No. 12, December 1983, pp. 11-14) for devising the figure. Lee's book, like so many others, doesn't do a good job on these concepts.

Of course, there is no substitute for IEEE Std 1364-2001 (and IEEE Std 1364.1-2002 defining the RTL subset).

Great reference for synthesizable verilog
This book is an excellent reference for writing synthesizable verilog. Chapter 4 (Best Known Methods for Synthesis) gives useful example and explaination on this matter.Such knowledge is usually only attainable through experience.

I find this book very useful, and would highly recommend it to students and new designers (even experienced designers too!). It will definitely help them in coding synthesizable verilog for tape-out!

No use !
Don't buy this book! Its useless, neither for beginners norfor advanced people(anyway). I went thru this book in couple of hours, found ridiciolous simple mistakes in it, Book has "for Syntheis" in its name but found so many rubbish pages full with some stupid simulation results. Well, one can find better docs on the Net just for free, instead of buying this book. ... Read more

Customer Reviews (1)

Good to have it
It is a handy book when you want to design a logical ciruit.It is mucheasier to simulate a circuit base on a simulation criteria than to build acircuit and experonce on that.

the book helps to learn about thesimulation concepts and much more... ... Read more

Product Description
Hardware Description Languages (HDLs) use statements, likeprogramming language statements, in order to define, simulate,synthesize, and layout hardware. One of the main HDLs is Verilog, awidely used and standardized language. Verilog can be used to designanything from the most complex ASIC to the least complex PAL. As ASICsand FPGAs become more complex, HDLs become a necessity for theirdesign. This course teaches how to use Verilog to design and simulatehardware. It begins by explaining the benefits of HDLs over otherdesign entry methods, including its ability to model different levelsof abstraction, its reusability, and documentability. Next, the syntaxof the Verilog language is explained in detail. By the end of thecourse, you will be able to design and simulate real hardware usingVerilog. The course includes the study guide, final exam, the textbookVerilog Designer’s Library (Prentice Hall, 1998) and one CD-ROMcontaining simulation software from Simucad, synthesis software from Synopsys and all of the code examples from the book. Upon successful completion the student receives 8 CEUs and a Certificate of Educational Achievement from the Institute of Electrical and Electronics Engineers. ... Read more

Product Description
Hardware description languages are used to design high density VLSI, allowing designers to put millions of transistors on a single substrate. Verilog is closing in on VHDL as the most popular of the hardware description languages. This is a tutorial in designing with Verilog. Each major chapter features in-depth Verilog examples of the coding described, and all the examples are assembled into a final full CPU design. ... Read more